This invention relates to a high integration density, vertical capacitor structure and a process for fabricating it, and more specifically, to a vertical capacitor structure formed in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer including a sinker doped region in contact with said buried doped layer and wherein an oxide trench structure is formed. The invention also relates to a process for integrating a vertical capacitor structure, starting from a structure blank which comprises a semiconductor substrate, a buried oxide layer and a buried doped layer.
As is well known, most integrated structures with capacitor functions are formed from polysilicon islands P, P1, P2 and/or metallizations that extend horizontally across a suitably oxidized silicon surface S, as shown schematically in FIG. 1.
A major drawback of such structures is the large silicon area they occupy by reason of their horizontal lay, especially where the structures involve high capacitances.
In some applications, such as DRAMs, a vertical type of capacitor structure is used in order to meet reduced silicon area requirements. Structures such as these are fabricated, for example, by providing dielectric trenches in a surface region of the DRAM device, specifically at the integration wells of the MOS components of the device. Structures thus obtained exhibit, however, low capacitances.
The underlying technical problem of this invention is to provide a vertical capacitor structure with such structural and functional features that high capacitance structures can be obtained while keeping the integration area small.
The disclosed embodiments of the present invention are directed to fabricating high integration density, vertical capacitor structures by utilizing dielectric trenches.
In one embodiment, the invention is directed to a vertical capacitor structure in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, and an oxide trench structure formed therein that is filled with suitably-doped polysilicon to produce, in combination with the sinker region, the plates of a vertical capacitor structure with the oxide trench structure providing the dielectric therebetween.
In accordance with another aspect of this embodiment of the invention, an electrically conductive region, such as polysilicon or metallization, extends over a plurality of vertical capacitors so formed to connect the underlying legs and thereby form a horizontal capacitor structure as well as a vertical capacitor structure.
In accordance with another embodiment of the invention, a process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer, and a buried doped layer is disclosed. The process includes defining a sinker region by forming a semiconductor layer, followed by oxidizing, first masking, depositing a thin pre-implanted oxide, n-type implanting, and thermally diffusing steps; defining an oxide trench structure by removing the oxide from the surface, growing an oxide layer, growing a nitride layer over the oxide layer, masking to define isolated regions, sequentially etching through the dielectric hard mask layer (the combination of the nitride and oxide layers) and the underlying silicon down to the buried oxide layer and oxidizing to grow oxide over the trench sidewalls; depositing doped polysilicon onto the whole surface to a thickness adequate to fill the trench oxidized during the previous step; and planarizing chemically the entire surface of the chip.
In accordance with another aspect of the foregoing process, the polysilicon is doped through discrete depositing steps by implanting enhancement dopant between the depositing steps. Alternatively, the polysilicon is doped in situ during a depositing step. Angled implantations may also be used.
In accordance with yet another embodiment of the invention, a vertical capacitor structure is provided that includes a semiconductor substrate, an oxide layer on the semiconductor substrate; a doped layer on the oxide layer; a semiconductor layer formed on the doped layer; and at least one trench structure formed in a semiconductor layer and filled with a doped region having a vertical central polysilicon region that is electrically isolated from the doped region that in turn communicates with the doped layer on the oxide layer.
In accordance with another aspect of this embodiment of the invention, a dielectric layer is formed between the polysilicon region and the doped region. Ideally, the dielectric layer is formed in contact with the oxide layer.